Many of devices using semiconductor IC logic circuits employ synchronous circuits rather than asynchronous circuits because the former are more reliable.
In the asynchronous system, when, for example, decoding counter outputs, if a time difference occurs between output bits as in a ripple counter, one-shot-like noise, which is referred to as "glitch", will occur each time a counter transition occurs. In the asynchronous system, therefore, delay times are obtained and timing is taken so as not to produce the glitches.
In the synchronous system, in response to successive input clocks, data is read into a latch circuit and then output to the following latch circuit via a target logic gate. This operation is performed sequentially. That is, in the synchronous system, data is entered in sequence to be operated upon and then data is entered again. Since such data entry is performed using the same clock, such a glitch as described above will not be produced. According to the synchronous system, processes such as logical operations, etc., can be performed dependably by merely making sure that the delay time associated with a logic gate located between latch circuits, is within the period of the clock input to the latch circuits.
In order to increase the reliability of operation, therefore, the synchronous system is used more frequently than the asynchronous system.
The performance of devices using the above-described synchronous system depends on the frequency of a clock signal synchronizing the devices, that is, the operating frequency. The operating frequency depends upon a delay time associated with a combinatorial circuit interposed between two latches or flip-flops formed within a semiconductor.
The shorter the above-described delay time, the higher the repetition frequency of the clock signal and the device's performance can be made. However, a plurality of logic circuits exist within an LSI and have different delay times. The maximum delay time will determine the repetition frequency of the clock signal. Thus, when one logic circuit is slow no matter how fast the other logic circuits are, the frequency of the clock signal has to be low, which causes a problem that the overall performance of the device is degraded. That is, in order to for the device to show its performance fully, it is necessary that combinatorial circuits have the same delay time and be fast.